Once Bittern, Twice Shy
Date:
HAFLANG presentation at the 20th anniversary edition of SPLS.
Custom hardware architectures for functional languages enjoyed a boom in the 80s and 90s following Backus’ Turing Award lecture “Can Programming Be Liberated from the von Neumann Style? A Functional Style and Its Algebra of Programs”. Research interest later waned due to difficulties in matching the rapid pace of RISC processor development and compiler techniques.
This talk from the HAFLANG project re-explores these ideas in a modern landscape — where single-thread performance of stock CPUs have begun to stagnate, but the performance of hardware prototyping platforms such as FPGAs have not. We present the Heron processor for evaluating non-strict functional programs, as well as its concurrent hardware garbage collector. While still slightly slower than conventional platforms, it offers interesting advantages in energy efficiency and opportunity for formal verification from source language down to hardware implementation. We also propose a path towards a single-chip many-core architecture.